This application is related to Korean Application No. 99-32908, filed Aug. 11, 1999, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices having on-chip error correction capability.
Due to the recent development of micro technology, semiconductor devices can be designed to be highly integrated and operate at high speed. Particularly for high integrated semiconductor memory devices, a high yield is desired.
A semiconductor memory device is composed of many memory cells. Among these memory cells, if even one memory cell does not properly operate, the overall semiconductor memory device cannot function properly. As the degree of integration of semiconductor memory devices increases, the probability that malfunction occurs in memory cells increases. Malfunction is caused by defects in the memory cells themselves or by soft errors resulting from the incidence of a particles. Malfunctioning damages the function of a semiconductor memory device and thus, is a principal cause of reduction in the yield of semiconductor memory devices.
To solve these problems, a technique of installing a redundancy circuit on a chip is widely used to substitute redundant cells for defective cells, thereby improving the yield. The redundancy circuit drives a redundancy memory cell block in which redundant cells are arranged in row and column directions, and selects a redundancy cell in the redundancy memory cell block for substituting for a defect cell. In other words, once an address signal designating a defective cell is input to the redundancy circuit, the redundancy circuit selects a redundancy memory cell for substituting for a normal memory cell having a defect.
In the conventional technology using the redundancy circuit, the number of redundancy memory cells is predetermined and the redundancy memory cells are disposed near to a memory cell block. In a case in which the number of defective cells exceeds the predetermined number of redundancy memory cells, some defective cells cannot be substituted for by redundancy memory cells. In such a case, a semiconductor memory device is finally determined to be bad and discarded. Accordingly, the improvement of the yield of semiconductor memory devices is limited.
There is another method of improving the yield of semiconductor memory devices. In this method, error check and correction (ECC) functions are installed in a semiconductor memory device. The technology related to the on-chip ECC is disclosed in U.S. Pat. No. 4,903,268. FIG. 1 of the xe2x80x2268 patent illustrates a syndrome generating circuit 7 that performs an exclusive-OR operation on the real check bits xe2x80x9cexe2x80x9d and the write check bits xe2x80x9cdxe2x80x9d.
U.S. Pat. No. 4,903,268 introduces a semiconductor memory device having on-chip ECC, in which data in a parity bit memory cell array can be independently accessed through switching means for external functionality testing of the parity bit memory cell array as well as a data bit memory cell array. The ECC of the U.S. Pat. No. 4,903,268 is usually effective in asynchronous semiconductor memory devices.
Another method for improving the yield of semiconductor memory devices is to combine the redundancy technique and the ECC technology, which is disclosed in an article by H. Kalter et al., entitled xe2x80x9cA 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, pp. 1118-1127 (1990). According to the H. Kalter et al. article, among all the outputs of the bit line sense amplifiers, which are activated in response to the activation of a single word line, that is, among 1112 bits, except for 16 bits, 1096 bits of redundant bit lines are included in eight ECC words each of which is composed of 128 data bits and 9 parity bits. In this method, since the number of bits of a single ECC word is large, an arithmetic logic block, which is necessary for checking bits for errors and determining the bits are normal or erroneous, is large and operation time is also long. Consequently, the method is not suitable for rapid operation. Therefore, an ECC circuit which does not impede the rapid operation of a synchronous semiconductor memory device is required.
Preferred integrated circuit memory devices comprise a memory cell array having therein a plurality of stored data bits and a plurality of parity bits generated from a plurality of write data bits received by the memory device during a write operation. The plurality of stored data bits and the plurality of parity bits may collectively form a word having a length of m+p bits, where m and p are integers. An error check circuit is also provided. The error check circuit converts the plurality of stored data bits and the plurality of parity bits into a plurality of syndrome bits (e.g., Si) that designate a location of a bit error in the plurality of stored data bits when compared against the original write data bits. These write data bits may be received by an input buffer within the memory device and the stored data bits may have error therein (relative to the write data bits) that was generated during the write operation. These preferred memory devices also preferably comprise an error correction circuit that uses the plurality of syndrome bits to correct an error in the plurality of stored data bits and after the correction generate a plurality of read data bits that match the plurality of original write data bits.
According to preferred aspects of these memory devices, the plurality of stored data bits and the plurality of parity bits collectively form an N-bit word (i.e., m+p=N). A binary value of the plurality of syndrome bits may also equal an integer n. Based on this arrangement, the error correction circuit may correct an error in the plurality of stored data bits by inverting an nth bit of the N-bit word and then passing the corrected word as a plurality of read data bits that match the plurality of write data bits. According to other preferred aspects of these devices, the plurality of syndrome bits are generated by providing the plurality of stored data bits and the plurality of parity bits to a plurality of logic gates that perform an exclusive OR operation. In particular, each of the plurality of logic gates has inputs that receive at least two of the plurality of stored data bits and at least one of the plurality of parity bits. The error correction circuit may also comprise a decoder that receives the plurality of syndrome bits and has a plurality of decoder outputs. This decoder may comprise a plurality of NAND gates that receive various combinations of the syndrome bits and inverted versions of the syndrome bits as inputs. The error correction circuit may also comprise a data correction circuit therein that receives the plurality of stored data bits and is electrically connected to the plurality of decoder outputs. A preferred data correction circuit may comprise a plurality of data correction units. Each data correction unit may receive a respective one of the plurality of stored data bits at a first input thereof and a respective one of the plurality of decoder outputs at a second input thereof.
According to still further embodiments of the present invention, a synchronous semiconductor memory device may be provided having a memory cell block with a plurality of memory cells, the memory cell block including a data bit memory cell array, which stores m data bits, and a parity bit memory cell array, which stores p parity bits, and an on-chip ECC circuit for checking and correcting errors of the (m+p) bits which are read from the memory cell block. The ECC circuit includes an error check circuit for selectively performing an exclusive OR operation with respect to the (m+p) bits to generate syndrome data, and an error correction circuit for correcting a data bit at a position corresponding to the syndrome data in the (m+p) bits. The (m+p) bits, which are provided to the error check circuit, are (m+p) bits read from the memory cell block and stored in a first pipeline stage in response to a first clock signal. The (m+p) bits, which are provided to the error correction circuit, are bits output from the first pipeline stage and stored in a second pipeline stage in response to a second clock signal.
The present invention also provides an error check and correction method in a synchronous semiconductor memory device having a memory cell block with a plurality of memory cells, the memory cell block comprising a data bit memory cell array, which stores m data bits, and a parity bit memory cell array, which stores p parity bits, and an on-chip ECC circuit for checking and correcting errors of the (m+p) bits which are read from the memory cell block. The method includes the steps of storing the m data bits, which are input to a DQ pad in response to a write command received in synchronization with a clock signal, and the p parity bits corresponding to the m data bits in the data bit memory cell array and the parity bit memory cell array, respectively; simultaneously reading the m data bits from the data bit memory cell array and the p parity bits from the parity bit memory cell array in response to a read command, which is received in synchronization with a clock signal, and outputting the (m+p) bits to a data line; transmitting the (m+p) bits over the data line to a first pipeline stage responsive to a first clock signal; providing an output of (m+p) bits of the first pipeline stage to an error check circuit and selectively performing an exclusive OR operation with respect to the (m+p) bits in response to a second clock signal to generate syndrome data; outputting the output of (m+p) bits of the first pipeline stage to a second pipeline stage responsive to the second clock signal; and providing an output of (m+p) bits of the second pipeline stage to an error correction circuit and correcting data of bits at positions corresponding to the syndrome data in the (m+p) bits.
As described above, the ECC circuit of a synchronous semiconductor device according to the present invention checks the output of the first pipeline stage, that is, an ECC word having a relatively small number of bits, for errors, and generates syndrome data, thereby reducing the overhead of an ECC operation block. Consequently, the ECC circuit does not impede the rapid operation of a pipeline.